In a complex integrated circuit such as a microprocessor, Programmable Logic Arrays (PLAs) typically have limited controllability of any input and are inaccessible at the outputs. This makes it very difficult to detect faults in the PLA, such as stuck-at faults, cross-point faults and bridging faults. It is, therefore, desirable to incorporate into the PLA some type of Design For Test technique, to allow for proper and complete testing. One such technique is a Built In Self Test (BIST) with input control generation approach.
The basic concept of BISTIG is to be able to assert exactly one row and exactly one product term at one time. In this way, all failures can be uncovered. Without a procedure like this, it is virtually impossible to fully test all failure modes because of the redundancies in a PLA that render some faults untestable. PLAs also contain a significant amount of reconvergent fanout which also makes it very difficult to fully verify the PLA.
In U.S. Pat. No. 4,672,610, a "Built in Self Test Input Generator" is described. However, that BISTIG was suitable for use in an integrated circuit fabricated using an NMOS process technology, and is less than ideal for use in an integrated circuit fabricated using CMOS process technology.